Server IP : 68.65.122.142  /  Your IP : 3.142.133.234
Web Server : LiteSpeed
System : Linux server167.web-hosting.com 4.18.0-513.18.1.lve.el8.x86_64 #1 SMP Thu Feb 22 12:55:50 UTC 2024 x86_64
User : glenirhm ( 1318)
PHP Version : 7.4.33
Disable Function : NONE
MySQL : OFF  |  cURL : ON  |  WGET : ON  |  Perl : ON  |  Python : ON
Directory (0755) :  /usr/share/locale/bo/../../mc/syntax/

[  Home  ][  C0mmand  ][  Upload File  ]

Current File : //usr/share/locale/bo/../../mc/syntax/vhdl.syntax
# Adam Pribyl, based on ADA
# modified: Andrew Borodin
# missing
# literal, on,  (something else)

caseinsensitive

context default

#wholechars abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ_

    keyword whole with yellow
    keyword whole select yellow
    keyword whole use yellow
    keyword whole is yellow
    keyword whole of yellow
    keyword whole length yellow
    keyword whole range yellow
    keyword whole left yellow
    keyword whole right yellow
    keyword whole delta yellow
    keyword whole return yellow
    keyword whole next yellow
    keyword whole null yellow
    keyword whole array yellow
    keyword whole downto yellow
    keyword whole to yellow
    keyword whole foreign yellow

# comment
    keyword -- magenta

# expressions
    keyword := brightgreen
    keyword . brightgreen
    keyword ; brightgreen
    keyword : brightgreen
    keyword , brightgreen
    keyword ' brightgreen
    keyword | brightgreen
    keyword ( brightgreen
    keyword ) brightgreen
    keyword [ brightgreen
    keyword ] brightgreen
    keyword \+ brightgreen
    keyword - brightgreen
    keyword / brightgreen
    keyword \* brightgreen
    keyword \*\* brightgreen
    keyword # brightgreen
    keyword & brightgreen
    keyword => brightgreen
    keyword < brightgreen
    keyword > brightgreen
    keyword <= brightgreen
    keyword >= brightgreen
    keyword = brightgreen
    keyword /= brightgreen

# operators and functions
    keyword whole sll green
    keyword whole srl green
    keyword whole sla green
    keyword whole sra green
    keyword whole rol green
    keyword whole ror green
    keyword whole rem green
    keyword whole mod green
    keyword whole not green
    keyword whole and green
    keyword whole nand green
    keyword whole or green
    keyword whole xor green
    keyword whole nor green
    keyword whole xnor green
    keyword whole abs green
    keyword whole new green

    keyword whole begin yellow
    keyword whole end yellow
    keyword whole exit yellow
    keyword whole for yellow
    keyword whole while yellow
    keyword whole if yellow
    keyword whole then yellow
    keyword whole else yellow
    keyword whole elsif yellow
    keyword whole case yellow
    keyword whole when yellow
    keyword whole with yellow
    keyword whole select yellow
    keyword whole assert yellow
    keyword    whole wait yellow
    keyword    whole open yellow
    keyword whole loop yellow
    keyword whole until yellow
    keyword whole others yellow
    keyword whole all yellow
    keyword whole block yellow
    keyword whole guarded yellow
    keyword whole after yellow
    keyword whole transport yellow
    keyword whole inertial yellow
    keyword whole reject yellow
    keyword whole unaffected yellow
    keyword whole disconnect yellow

# types and related stuff
    keyword whole integer cyan
    keyword whole natural cyan
    keyword whole positive cyan
    keyword whole string cyan
    keyword whole character cyan
    keyword whole boolean cyan
    keyword whole real cyan
    keyword whole bit cyan
    keyword whole bit_vector cyan
    keyword whole time cyan
    keyword whole units cyan
    keyword whole std_logic cyan
    keyword whole std_logic_vector cyan
    keyword whole severity_level cyan

# boolean values
    keyword whole true brightred
    keyword whole false brightred
# time values
    keyword whole fs brightred
    keyword whole ps brightred
    keyword whole ns brightred
    keyword whole us brightred
    keyword whole ms brightred
    keyword whole sec brightred
    keyword whole min brightred
    keyword whole hr brightred

# declarations
    keyword whole type brightcyan
    keyword whole subtype brightcyan

    keyword whole variable yellow
    keyword whole shared yellow
    keyword whole signal yellow
    keyword whole constant yellow
    keyword whole group yellow
    keyword whole file yellow
    keyword whole register yellow

    keyword whole port yellow
    keyword whole map yellow
    keyword whole label yellow
    keyword whole record yellow
    keyword whole generic yellow
    keyword whole alias yellow
    keyword whole attribute yellow

# ports
    keyword whole in white
    keyword whole out white
    keyword whole inout white
    keyword whole buffer white
    keyword whole linkage white
    keyword whole bus white

# library units
    keyword whole library yellow
    keyword whole entity yellow
    keyword whole architecture yellow
    keyword whole package yellow
    keyword whole body yellow
    keyword whole procedure yellow
    keyword whole function yellow
    keyword whole pure yellow
    keyword whole impure yellow
    keyword whole configuration yellow
    keyword whole component yellow
    keyword whole generic yellow
    keyword whole process yellow
    keyword whole postponded yellow
    keyword whole generate yellow

# reports
    keyword whole report red
    keyword whole severity red
    keyword whole note red
    keyword whole warning red
    keyword whole error red
    keyword whole failure red

# comment
context exclusive -- \n        magenta

context " " green